With electronic devices, particularly portable devices such as mobile phones, becoming smaller and yet at the same time offering a wider range of functions, there is a need to integrate multifunctional chips but without increasing the size of the devices and keeping a small form factor. Increasing the number of electronic components in a 2D structure is incompatible with these objectives, and therefore 3D packages are increasingly being adopted in order to provide greater functionality and higher component density but with a small form factor.
In a 3D structure electronic components such as semiconductor chips with different active IC devices may be provided in a multilayer stacked structure. Traditionally wire bonding (e.g., U.S. Pat. No. 6,933,172) is used to establish electrical interconnects between chips, but wire bonding requires greater in-plane size and out-of-plane size and is inconsistent with the objective of maximizing the component density. To connect electrically the components in different layers through-silicon-via (TSV) technology may be used to provide the electrical interconnect and to provide mechanical support. In TSV technology a via is fabricated in a silicon chip with different active IC devices or other devices fabricated by a semiconductor process and the via is filled with metal such as Cu, Au, W, solders, or a highly-doped semiconductor material such as polysilicon. The TSV can thus link bond pads on the top surface of the component with bond pads on the bottom surface of the component. Multiple components provided with such vias are then stacked and bonded together. Further important electrical paths through the electronic device can be shortened thus leading to faster operation.
While TSVs are frequently applied to electronic components they may also be applied to micromechanical components, such as MEMs devices.
FIGS. 1 (a) to (g) shows steps in a conventional method of forming a TSV for a NAND flash memory wafer.
In the step of FIG. 1 (a) the electronic device (in this case a memory wafer) is provided. The wafer has a first ‘upper’ surface 11 and a second ‘lower’ surface 12 opposite the first surface. The wafer comprises a silicon region 20 at an upper part of the wafer and an active region 30 at a lower part of the wafer. The active region comprises a bond pad 40. More particularly, in the illustrated example, the active region 40 comprises a plurality of electrical traces and/or conductive lines embedded in an isolation layer (e.g. SiO) 34 between the silicon region 20 and the bond pad 40. In the illustrated example, the active region 30 comprises a plurality of dielectric lines 32, polysilicon lines 36, and M4 lines 38 embedded in a silicon oxide isolation layer 34 between the silicon layer 20 and the bond pad 40. The bond pad is formed of metal and has a plurality of extending portions 39 which extend upwards into the silicon oxide region. The portions 39 may have particular structures and in the illustrated example these upwardly extending portions are T shaped, with the cross of the T being at the end remote from the bond pad.
FIGS. 1 (b) to 1(f) illustrate the method of forming the via-hole. In the step of FIG. 1 (b) a photo-resist layer 50 is added to protect parts of the device which are not to be etched; and a portion of the silicon layer 20 and a portion of the polysilicon layer 32 are removed by etching. In the step of FIG. 1 (c), a portion of the isolation layer 34 is removed by etching. In the step of FIG. 1 (d), a portion of the barrier metal layer M4 is removed by etching. In the step of FIG. 1 (e), a portion of the silicon oxide isolation layer is removed by etching. As can be seen in FIGS. 1 (b) to (e), the various layers are removed in separate etching steps. As the removed materials are different, a different etching process is needed for each. Furthermore, the width of etching in each step is substantially the same so that the via has a substantially uniform width. The fully formed via-hole 60 is shown in FIG. 1 (e). It extends from the top surface 11 of the device down to the bond pad 40 and has a substantially uniform width or diameter. However, the via-hole 60 does not extend through the bond pad 40.
In the step of FIG. 1 (e) an isolation layer 70 comprising a dielectric material is deposited inside the via-hole 60. The isolation layer 70 covers the inner sidewalls of the via-hole and extends over the top surface 11 of the silicon layer 20. In the step of FIG. 1 (g), electroplating is carried out to fill the via-hole with metal 82, 84. Usually the metal will be copper. The metal layer 82, 84 is solid and forms a T-shape. It comprises a vertical portion 84 in the via-hole and a horizontal or ‘cross’ portion 82 extending over the top surface 11 of the device. The bottom of the vertical portion of the electroplated metal 84 is in mechanical and electrical contact with the bond pad 40, but it is not integrally formed with the bond pad. That is, the via does not extend through the bond pad 40 and does not reach the second surface of the device 12. Even if the bond pad 40 and the electroplated layer 82, 84 are both made of copper, the two are not integral. They are separate pieces having different grain structures as a result of their different methods of manufacture (as the bond pad 40 is not formed by electroplating).
Forming the TSV in the above manner is a time consuming process as the etching has to be carried out in several different steps. Further, some of the etching steps should be carried out in different chambers or after evacuation of the room, in order to prevent contamination. This increases both the complexity of the method and the time required, thus increasing the cost of manufacture. Further, the above method may not always securely attach the electroplated layer 82, 84 to the bond pad or the side walls of the via-hole. This causes problems if stresses are applied to the device in manufacture or during use. Therefore, it is desirable to find faster and more cost efficient methods of forming vias and methods which ensure their mechanical integrity.